1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and to, for example, a technology effective if applied to an AC test technique for a semiconductor integrated circuit device equipped with a logic circuit having clock distribution routes with equivalent lengths.
2. Description of the Prior Art
Japanese Published Unexamined Patent Application No. Hei 07(1995)-084011 discloses a clock generator for scan test, which, in order to perform a scan test on an internal logic circuit in a short period of time, combines signals A, B and C formed by dividing a continuous clock and thereby generates a first scan test clock inputted to a slave latch of a scan test circuit constituted by latches in which flip-flops are connected in series, and a second scan test clock inputted to a master latch of the scan test circuit. A technology for forming each internal clock using a PLL circuit, causing a combination circuit to output a first clock pulse corresponding to the internal clock in a test mode to transmit an input signal to a logic stage used as a combination circuit, generating a second clock pulse corresponding to the internal clock to fetch an output signal of the logic stage into its corresponding flip-flop FF, thereby recovering a test result by use of a scan circuit has been disclosed in Japanese Published Unexamined Patent Application No. Hei 2001-091590.